Toshiba claims to reduce standby power by 85%

March 2, 2013, By Sanjeev Ramachandran

Toshiba has claimed to have successfully tested a low-power embedded SRAM memory chip that reduces power consumption by up to 85%. The chip maker giant announced at the IEEE International Solid State Circuit Conference that it had developed an SRAM chip that can reduce both active and standby power consumption by 27% and 85% respectively.

The BLPC predicts power consumption of bit lines by using replicated bit lines to monitor the frequency of the ring oscillator. It minimizes the active power of the SRAM in certain conditions by monitoring the current consumption of the SRAM rest circuits.

The DCRC decreases standby power in the retention circuit considerably by periodically activating itself to update the size of the buffer of the retention driver.


According to Toshiba, as low performance applications require only tens of MHz operations, SRAM temperature remains around room temperature, where active and leakage power consumptions are comparable. Given this, the key issue is to reduce active and standby power from high temperature to room temperature.

Toshiba did not indicate how soon the technique might be deployed in commercial logic or memory components. But according to them, its SRAM chips can be used in smartphones. But intensive testing would be required before the chips are available commercially.

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