Intel Transactional Memory Support for Haswell Round the Bend

February 10, 2012, By Sanjeev Ramachandran

The technique of transactional memory is one step closer to becoming widely popular, with Intel announcing that its Haswell architecture will include hardware support for transactional memory when it ships sometime next year.

Multi-thread programs are made easier with the help of transactional memory; complex operations can be performed concurrently, in isolation from each other, with those operations either completing or being undone as if they’d never been started.

In traditional multi-threaded software, programs protect shared with locks and only the single thread holding the lock can control the shared resource at one time.

But transactional memory kind of bypasses the issue of lock.  They start a transaction before attempting any modification to the structure, make their changes, and when they’ve finished, commit the transaction. During the transaction, the transactional memory system takes note of all the memory that the thread reads and writes.

When the transaction is committed, the system checks that no other thread made any changes to the memory the transaction used. If there were no changes, the transaction is committed and the thread continues. If there were changes, the transaction is aborted, and all its changes are undone.

Haswell’s transactional support, or the Transactional Synchronization Extensions (TSX), come in two parts: HLE and RTM. Basically, operating systems implement locks with pieces of memory, typically using the processor’s natural integer type.

The thread taking the lock does something along the lines of incrementing its value from 0 to 1. To release the lock, the operation is reversed, for example, decrementing from 1 to 0.

These modifications are visible to every processor core and thread in the system, and if another thread sees that the value in our example is 1, it knows it cannot take the lock, and must instead wait for it to go back to 0.

Between acquiring the lock and releasing it, the processor tracks all the memory that the threads read and write. If two threads modify the same piece of memory, or one thread reads a value that a second thread changes, the processor will abort the transaction when the lock is released. If there are no conflicts, however, execution continues normally.

Where HLE implicitly uses transactions to allow lock-based code to run concurrently, RTM makes the starting, committing, and aborting transactions explicit. Whenever a thread starts a transaction with the new XBEGIN instruction, it also specifies a “fallback” routine that will execute if the transaction fails.

When the transaction is ended, with the new XEND instruction, the processor commits the transaction if there were no conflicts, or aborts it and switches to the fallback routine if there were. Transactions can also be aborted explicitly by software with a new XABORT instruction.

So Intel’s offering something short of full transactional memory. An implementation could, in principle, always use the fallback path. However, the company expects Haswell to support transactions most of the time, provided the applications do not attempt to perform certain forbidden operations within a transaction.

With Intel’s initiative, the technique of transactional memory is becoming more than just experimental, ready to feature in a mainstream, mass-market processor.

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